In the current IC fabrication process, semiconductor testing plays an important role. After complicated semiconductor fabrication procedures of a batch of wafers have been finished, they are sent to the testing stage. Meanwhile, it is necessary to perform test of each die to discriminate quality of dies on each wafer. After packaging of normal dies is finished, commercial products in the market are obtained. Through the steps of electric or physical test of semiconductor, dies not up to the specification are immediately discarded, to avoid waste of production cost and time, thereby enhancing production efficiency, greatly increasing the yield of production and ensuring the quality of product.
The test interface of existent testers only uses simple test connection signals. There is no test mark signal and determination and protection circuit. As shown in FIG. 1, because wafers are tested by a semiconductor test system having no discrimination and protection functions, erroneous classification of IC may easily occur. Moreover, when performing multi-chip test, erroneous connection of the interface connection may occur due to man-made carelessness. If test is performed without immediately finding the error, incorrect test results will be obtained without self-awareness. If bad products are shipped to customers, not only will they be returned, but the business credit will also be badly affected.
The conventional test flowchart in FIG. 1 will be described in detail below. First, a finished wafer is prepared to be sent to a semiconductor test machine before test (Step 10). When a prober detects the position of a measurement point, it sends out a start signal (Step 11). A tester then receives the start signal to start the test (Step 12). Next, after the tester has finished the test, it sends out the test result (Bin) signal (Step 13). Subsequently, the tester sends out an end of test (EOT) signal again (Step 14), and the prober receives the Bin signal and the EOT signal (Step 15). Whether the test of the whole wafer is finished is checked (Step 16). If the answer is yes, the test of the next wafer is then performed; otherwise, it is necessary to feedback a signal to Step 11, and Steps 11 to 16 needs to be repeated. The test of the next wafer can be performed only after the test of each die of the whole wafer has been finished. Meanwhile, whether the tested wafer is the last one is checked. That is, whether the test of all the batch of wafers has been finished is checked (Step 17). If the test of the all batch of wafers has been finished, the test ends (Step 18). Otherwise, Steps 11 to 17 are repeated. During the test process, only simple test connection signals like the start signal, the Bin signal and the EOT signal. There is no circuit having discrimination and protection functions. Therefore, erroneous classification of IC may easily arise.
Accordingly, the present invention aims to propose a semiconductor test system having a tester and a prober and having discrimination and protection functions and the test method thereof to resolve the problems in the prior art.